1. Technical Field
The present invention relates generally to integrated circuits, and more particularly, to an error correcting logic system.
The present invention also relates to a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
2. Related Art
As integrated circuits (IC) have continued to diminish in size, they have become more sensitive to radiation induced soft errors. A “soft error” is an interruption of a circuit in the absence of any manufacturing defects and results in a false or invalid output even with stable inputs. Soft errors are sometimes referred to as single event upsets (SEU) and usually are associated with an SRAM cell where a single radiation event can cause the cell to be upset and hold the incorrect data. These radiation events can come from alpha (α) particles from decaying lead present in package interconnects, or from cosmic radiation from deep space. The incidence of a radiation event causes an injection of current on the nodes of integrated circuits. The amount of charge to cause a circuit failure due to this injected current is called the critical charge (Qcrit). As ICs continue to scale in size, the Qcrit of circuits is becoming smaller and more circuits are becoming sensitive to radiation events. This includes circuits such as latches, register files and dynamic logic systems. Dynamic logic systems have also found increased usage because they are faster in some implementations. However, such systems are more unstable than static systems, and also more susceptible to soft error-induced and other types of electrical faults. One reason these systems are more unstable and fault intolerant is that faults propagate through them very easily because opposing currents are minimized to enhance performance. Once an error occurs in a dynamic logic system, the system is not recoverable as in a static circuit.
A common approach to addressing soft errors is the development of fault tolerant system designs that employ redundant or spare logic units. In one such approach, a system is designed to include at least three identical logic units, which operate in parallel, and the respective outputs of the units are polled to determine the correct output data. Specifically, if the results of the poll reveal that at least two of the three units output majority data, then such identical data is assumed correct. While this approach will provide relatively accurate output data, the approach is disadvantageous because it requires employing at least three separate redundant units, each designed to output the same data. Further, this approach adds size and power to the overall design. In addition, this approach does not address the extremely rapid propagation of a fault through the IC.
In another approach, a fault tolerant system employs only two units, which operate in parallel. In this system, the respective outputs of the two units are compared, and if they do not match, then a known signature is employed through both systems in an attempt to determine the correct and faulty outputs. This system is also disadvantageous in that several clock cycles must be performed when the unit outputs do not match, thereby decreasing the operating throughput of the system. This approach also does not address the extremely rapid propagation of a fault through the IC.
In view of the foregoing, there is a need in the art for an error correcting logic system that does not suffer from the problems of the related art.